Efficient Block Codes for Error Correction Using Low Density Parity Check Codes

This paper presents a novel high-speed BCH (hamming) decoder that corrects single-bit errors in parallel and multiple-bit errors corrects serial manner. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and multiple errors occur at a higher probability. To prevent such soft or transient fault related attacks, we consider fault tolerance as a method of mitigation. Most of the current fault tolerant schemes are only multiple bit error detectable but not multiple bit error correctable. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH based hamming decoders capable of correcting any multiple bit error. This error detection and correction algorithm is synthesized and simulated by using XILINX ISE.